1. Field of the Invention
The present invention relates to an input/output device which performs the input/output of internal and external signals to and from equipment, and particularly to input/output ports in a semiconductor device.
2. Description of Related Art
When equipment such as a motor requiring a large current is directly driven, a technique for driving a plurality of input/output ports by signals changed at the same logic level and making their input/output devices conductive to the outside with respect to each other to thereby take out a large current has been used in a semiconductor device. A problem arises in that when the setting of the input/output at the respective input/output devices is programmable and the plurality of input/output devices are made conductive to the outside, a large current flows between the input/output devices when levels of other polarity are outputted to the respective input/output devices due to programming glitches or the like, thereby causing the fear of occurrence of breakdowns in the input/output devices.
With a view toward solving such a problem, there has been invented a technique about a semiconductor integrated device, which has been disclosed in Japanese unexamined patent publication No. 1986(S61)-156918. The semiconductor integrated device of this disclosure shown in FIG. 11 has three CMOS inverters (105, 106), (108, 109) and (113, 114), two transfer gates 102 and 115, and two initial value setting circuits 104 and (116, 111). A positive voltage is applied to source terminals 101 and 112, and an input signal is applied to a signal input terminal 107. The transfer gates 102 and 105 are brought into conduction when their control input terminals are low and high levels, respectively, whereas when they are brought into non-conduction when the control input terminals are high and low levels, respectively.
Let's assume that when a signal output terminal 110 is of a high level, the signal output terminal 110 is short-circuited to a ground potential. In this case, the transistors 105 and 108 are both in an operating state. Thus, the input of the inputs of the NOR gate 104, which is supplied from the transistor 105, becomes low in level and its output is brought to a high level. Therefore, the transfer gate 102 is brought to a non-conducting state. Thus, a current path extending from the source terminal 101 to the transistor 108 via the transfer gate 102 and extending from the signal output terminal 110 to the ground potential is interrupted or cut off, thus suppressing the flow of a large current through the current path.
Let's assume that when the signal output terminal 110 is low in level, the signal output terminal 110 is short-circuited to the source potential. In this case, the transistors 109 and 114 are both in an operating state. Accordingly, since the inputs of the NAND gate 111 are both rendered high in level and its output is rendered low in level, the transfer gate 115 is placed in an interruption state. Thus, a current path extending from the signal output terminal 110 to the ground potential via the transistor 109 and the transfer gate 115 is interrupted to suppress the flow of a large current through the current path.
That is, the short-circuited state of the signal output terminal 110 is detected and hence the transfer gates 102 and 115 are cut off or interrupted in the semiconductor device. It is thus possible to suppress the flow of an excessive current through the CMOS inverters (108 and 109) and by extension prevent their breakages.